DESIGN FOR IDDQ TESTABILITY PDF

Such an increase of current might be owed to a physical defect of the chip. Nevertheless, it is conceivable that despite the defect the functional behavior of the chip is correct. Thus the method of IDDQ testing is rather a defect oriented method than an error oriented method. It may also be used to improve the reliability of chips section Within the model of IDDQ faults all conceivable faults are considered which may increase power consumption. For example, the fault model includes bridging faults, gate ox- ide shorts, transistor stuck on faults, and some stuck at faults.

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Such an increase of current might be owed to a physical defect of the chip. Nevertheless, it is conceivable that despite the defect the functional behavior of the chip is correct. Thus the method of IDDQ testing is rather a defect oriented method than an error oriented method.

It may also be used to improve the reliability of chips section Within the model of IDDQ faults all conceivable faults are considered which may increase power consumption. For example, the fault model includes bridging faults, gate ox- ide shorts, transistor stuck on faults, and some stuck at faults. Functional Undetectable Defects With functional tests one tries to stimulate a fault and to propagate resulting erroneous signals to a primary output.

In any stable state exactly one of the two transistors is conducting and therefore the output y is either connected to VDD or to VSS. Depending on the resistance of transistor channels, the value of the output signal y results from the voltage divider built by T1 and T2. It is also possible that despite the fault the voltage at the output y may be interpreted as the correct logic value. Thus the logical behavior of the circuit may be correct. However, because of the effect of electron migration the fault may later cause fail- ures after a longer period of operation.

Therefore on using the IDDQ test it is possible to detect defects that can not yet be detected by functional tests. An increased current can even be caused by a transistor stuck open fault.

Here the n-transistor is well suited to transmit the value 0 and the p- transistor is well suited to transmit 1. As a consequence it may happen that the transistor T3 of the succeeding inverter is not perfectly locked, and therefore there is an erroneous current between VDD and VSS. Often such faults are also detected by functional tests as stuck at faults.

Further faults that cause an increase of quiescent current are bridging faults, and gate oxide shorts. This shall be demonstrated for the example of a hard combinatorial bridging fault section This will cause a high current because of the short circuit. For an automatic IDDQ test pattern generation with common test pattern generators it is very easy to model the bridging fault.

Each pattern producing the signal 1 at the new output can be used as a test pattern. Since for computing IDDQ test patterns fault propagation can be omitted, there are more possible test patterns for a fault than for functional tests. Thus an IDDQ test needs fewer test patterns. Thus for a given number of measurements one determines a set of test patterns obtaining a maximal fault coverage. Since the model of stuck at faults does not deter- mine a unique kind of physical defect, some stuck at faults might increase quiescent current, whilest others do not.

But this may not be true for an interruption of a wire. Thus the IDDQ method cannot replace functional tests but can extend such tests to improve defect coverage. One should never use IDDQ measurements to reduce the number of functional test patterns.

If all stuck at faults could be detected by IDDQ measurements then the circuits obtained would be completely testable for stuck at faults with only two test patterns. Multiple faults do not cause additional problems for IDDQ testing. For example it can be shown that when simple design rules are respected [ IDDQ test pattern generation also has to calculate the intensity of quiescent current.

For this one may use an extended switch level simulation also considering realistic resistances of transistors. On the other hand, such simulations can also be used to determine the accuracy needed for an IDDQ measurement. In order to receive meaningful results IDDQ tests should be restricted to such test patterns producing a low power consumption for correct chips. Section Applying the same test pattern to several correct chips one obtains different measured current values.

Figure The average value of that distribution denotes the typical quiescent current of a correct chip. But be- cause of deviations during manufacture actual values will differ from the expected value. The threshold value for an IDDQ measurement should be determined according to the expected erroneous current. Then one has to compare the costs of both kinds of erroneous decisions: What are the expected costs if a defect chip remains undetected and what does is cost to classify a correct chip as faulty?

But since such a resistor within a supply line will reduce the applied voltage it has to be shorted by a transistor for normal operation of the chip. As an alternative approach the resistor can be re- placed by a capacitor. Again, for normal operation it is shorted and unloaded.

For testing, the transistor is opened and the capacitor is loaded by the quiescent current. If it extends a certain threshold value the chip fails the IDDQ test. In [ This way it is possible to perform an IDDQ test without hardware overhead.

With this technique self-tests are also possible. For example, as mentioned above, the correct circuit should have a very low quiescent current such that the erroneous current is easily detectable. Therefore the circuit may not use oscillators, and whenever there are dynamic storage blocks they have to be separated for the test.

Also pull up resistors have to be disabled for the test mode, and for pad drivers, analog cells, and bipolar sub- circuits a separate power supply is needed because they typically have a high power consumption. Otherwise additional drivers have to be provided to force buses to default values whenever there is no actual write operation.

Because of the necessary time for exact current measurement the circuit must be able to work at a slow clock rate. Therefore if the chip itself is monitoring the system clock this must be deactivated for the test. Furthermore, for regular structured circuits such as storage blocks, IDDQ tests are not of interest be- cause there are already specialized tests available with high defect coverage.

Further Parameter Tests Since one reason for an increased quiescent current is that of illegal signal levels, the observation of voltage levels at critical signals is also an alternative to IDDQ tests.

In section Of course faults can also cause an increased current during the phase transient states. To discover such effects one uses IDDT tests, observing transient current.

For example, in [ In particular, it is suitable for chips with low power supply. For this task a method is described in [ Related posts:.

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Design for testing

Taujind Nevertheless, it is conceivable that despite the defect the functional behavior of the chip is correct. Also pul l up resistors have to be disabled for the test fo, and for pa d drivers, analog cells, and bipolar sub- circuits a separate power supply is needed because they typically have a high power consumption. I hope you got it. To discover such effects one testabllity IDD T tests, observing t r ansient cur r en t. For this task a method is described in [ Such an increase of current might be owed to a physical defect of the chip. Of course faults can also cause an increased current during the phase transient states.

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DESIGN FOR IDDQ TESTABILITY PDF

The design modifications can be strictly physical in nature e. While controllability and observability improvements for internal circuit elements definitely are important for test, they are not the only type of DFT. Other guidelines, for example, deal with the electromechanical characteristics of the interface between the product under test and the test equipment. Examples are guidelines for the size, shape, and spacing of probe points, or the suggestion to add a high-impedance state to drivers attached to probed nets such that the risk of damage from back-driving is mitigated. The common understanding of DFT in the context of Electronic Design Automation EDA for modern microelectronics is shaped to a large extent by the capabilities of commercial DFT software tools as well as by the expertise and experience of a professional community of DFT engineers researching, developing, and using such tools. Objectives of DFT for microelectronics products[ edit ] DFT affects and depends on the methods used for test development, test application, and diagnostics. Most tool-supported DFT practiced in the industry today, at least for digital circuits, is predicated on a Structural test paradigm.

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Then one has to compare the costs of both kinds of erroneous decisions: For example, in [ This shall be demonstrated for the e xample of a hard combinatorial bridgin g fault section It may also be used to improve the r eliabilit y of chips section But since such a resistor within a supply line will reduce the applied voltage it has to be shorted by a transistor for normal operation of the chip. As an alternative approach the resistor can be re- placed by a capacitor. I am very confused. Of course faults can also cause an increased current during the phase transient states. If you have any example then it would be more clear. PV charger battery circuit 4.

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